ATmega128
or cleared by manipulating the T W I Control Register (T W CR). W hen in Transmitter mode, the
value of the received (N)ACK bit can be determined by the value in the T W SR.
The START/STOP Controller is responsible for generation and detection of START, REPEATED
START, and STOP conditions. The START/STOP controller is able to detect START and STOP
conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up
if addressed by a master.
If the T W I has initiated a transmission as master, the Arbitration Detection hardware continu-
ously monitors the transmission trying to determine if arbitration is in process. If the T W I has lost
an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate
status codes generated.
Address Match Unit
Control Unit
The Address Match unit checks if received address bytes match the 7-bit address in the T W I
Address Register (T W AR). If the T W I General Call Recognition Enable (T W GCE) bit in the
T W AR is written to one, all incoming address bits will also be compared against the General Call
address. Upon an address match, the Control Unit is informed, allowing correct action to be
taken. The T W I may or may not acknowledge its address, depending on settings in the T W CR.
The Address Match unit is able to compare addresses even when the AVR MCU is in sleep
mode, enabling the MCU to wake up if addressed by a master. If another interrupt (e.g., INT0)
occurs during T W I Power-down address match and wakes up the CPU, the T W I aborts opera-
tion and return to it’s idle state. If this cause any problems, ensure that T W I Address Match is the
only enabled interrupt when entering Power-down.
The Control unit monitors the T W I bus and generates responses corresponding to settings in the
T W I Control Register (T W CR). W hen an event requiring the attention of the application occurs
on the T W I bus, the T W I Interrupt Flag (T W INT) is asserted. In the next clock cycle, the T W I Sta-
tus Register (T W SR) is updated with a status code identifying the event. The T W SR only
contains relevant status information when the T W I Interrupt Flag is asserted. At all other times,
the T W SR contains a special status code indicating that no relevant status information is avail-
able. As long as the T W INT flag is set, the SCL line is held low. This allows the application
software to complete its tasks before allowing the T W I transmission to continue.
The T W INT flag is set in the following situations:
?
?
?
?
?
?
?
?
After the T W I has transmitted a START/REPEATED START condition
After the T W I has transmitted SLA+R/ W
After the T W I has transmitted an address byte
After the T W I has lost arbitration
After the T W I has been addressed by own slave address or general call
After the T W I has received a data byte
After a STOP or REPEATED START has been received while still addressed as a slave
W hen a bus error has occurred due to an illegal START or STOP condition
204
2467X–AVR–06/11
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